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MT6223 GSM/GPRS Baseband Processor Technical Brief
Revision 1.02
Jun 13, 2007
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Revision History
Revision 1.00 1.01 1.02 1.03 Date Jun 7th, 2007 Jun 13, 2007 Jun 14, 2007 Comments May29, 2007 First Release Add MT6223P product branch 1. Correct the typo in row number of TFBGA dimension 2. BPI_BUS2 should be placed in ball number R3, and number U2 have no ball out 1. Modify TFBGA diagram figure
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TABLE OF CONTENTS Revision History ..................................................................................................................................................................... 2 1. System Overview ............................................................................................................................................................. 5 1.1 Platform Features ....................................................................................................................................................... 8 1.2 MODEM Features.................................................................................................................................................... 10 1.3 Multi-Media Features................................................................................................................................................11 1.4 General Description ................................................................................................................................................. 12 Product Descriptions..................................................................................................................................................... 14 2.1 Pin Outs.................................................................................................................................................................... 14 2.2 Top Marking Definition ........................................................................................................................................... 16 2.3 Pin Description......................................................................................................................................................... 19
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1. System Overview
MT6223 is an entry level chipset solution with class 12 GPRS/GSM modem. It integrates only only analog baseband but also power management blocks into one chip and can greatly reduce the component count and make smaller PCB size. Besides, MT6223 is capable of SAIC (Single Antenna Interference Cancellation) and AMR speech. Based on 32 bit ARM7EJ-S for high quality modem performance. Typical application diagram is shown in Figure 1. Platform MT6223 runs the ARM7EJ-S
TM TM
Multi-media MT6223 utilize high resolution audio DAC, digital audio, and audio synthesis technology to provide superior audio features., e.g. MP3 ring tone. For MT6223P, MP3 player is also supported. Connectivity, and Storage MT6223 supports UART as well as Bluetooth interface. Also, necessary peripheral blocks are embedded for a voice centric phone: Keypad Scanner with the capability to detect multiple key presses, SIM Controller, Alerter, Real Time Clock, PWM, Serial LCD Controller, and General Purpose Programmable I/Os. Furthermore, to provide more configuration and bandwidth for display, an additional 9-bit parallel interface is incorporated. For MT6223P, software memory card control is provided through LCD interface, including SD and mini SD, etc. Therefore high quality MP3 playback of 48kHz sampling with 320kbps format can be supported Audio Using a highly integrated mixed-signal Audio Front-End, architecture of MT6223 allows for easy audio interfacing with direct connection to the audio transducers. The audio interface integrates D/A and A/D Converters for Voice band, as well as high resolution Stereo D/A Converters for Audio band. In addition, MT6223 also provides Stereo Input and Analog Mux. MT6223 also supports AMR codec to adaptively optimize speech and audio quality. Radio MT6223 integrates a mixed-signal Baseband front-end in order to provide a well-organized radio interface with flexibility for efficient customization. It contains gain and offset calibration mechanisms, and filters with programmable coefficients for comprehensive compatibility control on RF modules. This approach also allows the usage of a high resolution D/A Converter for controlling VCXO or crystal, thus reducing the need for expensive TCVCXO. MT6223 achieve great MODEM performance by utilizing 14-bit high resolution A/D Converter in the RF downlink path. Furthermore, to reduce the need for extra external current-driving
RISC
processor, MT6223 provides an unprecedented platform
RISC processor at up to
52Mhz, thus providing best trade-off between system performance and power consumption. For large amount of data transfer, high performance DMA (Direct Memory Access) with hardware flow control is implemented, which greatly enhances the data movement speed while reducing MCU processing load. Targeted as a modem-centric platform for mobile applications, MT6223 also provides hardware security digital rights management for copyright protection. For further safeguarding, and to protect manufacturer's development investment, hardware flash content protection is also provided to prevent unauthorized porting of software load. Memory MT6223 supports up to 4 external state-of-the-art devices through its 8/16-bit host interface. Devices such as burst/page mode Flash, page mode SRAM, and Pseudo SRAM are supported including ADMUX type devices. For greatest compatibility, the memory interface can also be used to connect to legacy devices such as Color/Parallel LCD, and multi-media companion chip are all supported through this interface. To minimize power consumption and ensure low noise, this interface is designed for flexible I/O voltage and allows lowering of supply voltage down to 1.8V. The driving strength is configurable for signal integrity adjustment. The data bus also employs retention technology to prevent the bus from floating during turn over.
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component, the driving strength of some BPI outputs is designed to be configurable. Debug Function The JTAG interface enables in-circuit debugging of software program with the ARM7EJ-S core. With this standardized debugging interface, MT6223 provides developers with a wide set of options in choosing ARM development kits from different third party vendors. Low Power Features MT6223 offers various low-power features to help reduce system power consumption. These features include Pause Mode of 32KHz clocking at Standby State, Power Down Mode for individual peripherals, and Processor Sleep Mode. In addition, MT6223 are also fabricated in advanced low leakage CMOS process, hence providing an overall ultra low leakage solution. Power Management MT6223 integrates all regulators that a voice-centric phone needs. Seven LDOs optimized for Specific
GSM/GPRS baseband sub-systems are included, and a RF transceiver needed LDO is also built-in. Besides Li-Ion battery charge function, SIM card level shifter interface, two open-drain output switches to control the LED and vibrator schemes are equipped. as Other power overload management such thermal
protection, Under Voltage Lock-out Protection (UVLO), over voltage protection and oower-on reset and start-up timer are also MT6223 features. Besides, 3 NMOS switches controlling the RGB LEDs are also embedded to reduce BOM coount. Package The MT6223 device is offered in 9mmx9mm, 224-ball, 0.5 mm pitch, TFBGA package.
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FLASH SRAM PSRAM ADMUX
(MT6223P only) LCD MEMORY CARD
DEBUGGER
JTAG
EXTERNAL MEMORY INTERFACE
9-BIT PARALLEL INTERFACE
AFC
TCVCXO
SYSCLK SPEECH/AUDIO INPUT SPEECH/AUDIO OUTPUT FM STEREO RADIO INPUT APC TRX I/Q BPI BSI RF MODULE
MT6223
AUXADC CHIP UID SUPPLY VOLTAGES POWER MANAGEMENT CIRCUITRY RGB SERIAL LCD UART KEYPAD
HIFI STEREO OUTPUT ALERTER PWM I2S SIM USIM
CHARGER
AUDIO DAC
SERIAL LCD
1 4 7 *
2 5 8 0
3 6 9 #
Figure 1 Typical application of MT6223.
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1.1
Platform Features
Integrated voice-band, audio-band base-band analog front ends and
User Interfaces 5-row x 7-column keypad controller with hardware scanner Supports multiple key presses for gaming SIM/USIM Controller with hardware T=0/T=1 protocol control Real Time Clock (RTC) operating with a separate power supply General Purpose I/Os (GPIOs) 2 Sets of Pulse Width Modulation (PWM) Output Alerter Output with Enhanced PWM or PDM 6 external interrupt lines Security Supports security key and 59 bit chip unique ID Connectivity
General
TFBGA 9mmx9mm, 224-ball, 0.5 mm pitch package MCU Subsystem ARM7EJ-S 32-bit RISC processor High performance multi-layer AMBA bus Java hardware acceleration for fast Java-based games and applets Operating frequency: 26/52 MHz Dedicated DMA bus 7 DMA channels 320K bits on-chip SRAM On-chip boot Programming ROM for Factory Flash
3 UARTs with hardware flow control and speed up to 921600 bps DAI/PCM and application Memory card MT6223P Low Power Schemes Power Down Mode for analog and digital circuits Processor Sleep Mode Pause Mode of 32KHz clocking at Standby State 3-channel Auxiliary 10-bit A/D Converter for application usage other than battery monitoring Power and Supply Management 2.8V to 5.5V Input Range Charger Input up to 8V Seven LDOs Optimized for Specific GSM Sub-systems One LDO for RF transceiver I2S interface for Audio
Watchdog timer for system crash recovery 3 sets of General Purpose Timer Circuit Switch Data coprocessor Division coprocessor External Memory Interface Supports up to 4 external devices Supports 8-bit or 16-bit memory components with maximum size of up to 32M Bytes each Supports Flash and SRAM/PSRAM with Page Mode or Burst Mode Supports ADMUX Industry standard 9-bit Parallel LCD Interface Supports multi-media companion chips with 8/16 bits data width Flexible I/O voltage of 1.8V ~ 2.8V for memory interface Configurable driving strength for memory interface
interface
is
provided
for
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High Operation Efficiency and Low Stand-by Current Li-Ion Battery Charge function SIM Card Interface Two Open-Drain Output Switches to Control the LED and Vibrator Three NMOS switches to control RGB LEDs Thermal Overload Protection
Under Voltage Lock-out Protection Over Voltage Protection Power-on Reset and Start-up Timer Test and Debug Built-in digital and analog loop back modes for both Audio and Baseband Front-End DAI port complying with GSM Rec.11.10 JTAG port for debugging embedded MCU
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1.2
MODEM Features
GMSK modulator with analog I and Q channel outputs 10-bit D/A Converter for uplink baseband I and Q signals 14-bit high resolution A/D Converter for downlink baseband I and Q signals Calibration mechanism of offset and gain mismatch for baseband A/D Converter and D/A Converter 10-bit D/A Converter for Automatic Power Control 13-bit high resolution D/A Converter for Automatic Frequency Control Programmable Radio RX filter with adaptive bandwidth control Dedicated Rx filter for FB acquisition 2 Channels Baseband Serial Interface (BSI) with 3-wire control Bi-directional BSI interface. RF chip register read access with 3-wire or 4-wire interface. 10-Pin Baseband Parallel Interface (BPI) with programmable driving strength Multi-band support
GSM channel coding, equalization and A5/1, A5/2 and A5/3 ciphering GPRS GEA1, GEA2 and GEA3 ciphering Programmable GSM/GPRS Modem GSM Circuit Switch Data GPRS Class 12 Voice Interface and Voice Front End Two microphone inputs sharing one low noise amplifier with programmable gain and automatic gain control (AGC) mechanism Voice power amplifier with programmable gain 2nd order Sigma-Delta A/D Converter for voice uplink path D/A Converter for voice downlink path Supports half-duplex hands-free operation Compliant with GSM 03.50
Radio Interface and Baseband Front End
Voice and Modem CODEC Dial tone generation Voice Memo Noise Reduction Echo Suppression Advanced Sidetone Oscillation Reduction Digital sidetone generator with programmable gain Two programmable acoustic compensation filters GSM/GPRS quad vocoders for adaptive multirate (AMR), enhanced full rate (EFR), full rate (FR) and half rate (HR)
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1.3
Multi-Media Features
Dedicated Parallel Interface supports 2 external 8/9 bit Parallel Interface, and Serial interface for LCM For MT6223P, memory card interface is shared with LCD interface. And the software memory card control is available for MP3 playback
LCD Interface
LCD Controller Supports simultaneous connection to up to 3 parallel LCD or 2 serial LCD modules Supports LCM format: RGB332, RGB444, RGB565, RGB666, RGB888 Supports LCD module with resolution up to 176x220 at 24bpp 2 layer blending Supports hardware display rotation for each layer Audio CODEC Wavetable synthesis with up to 64 tones Advanced wavetable synthesizer capable of generating simulated stereo Wavetable including GM full set of 128 instruments and 47 sets of percussions PCM Playback and Record Digital Audio Playback Audio Interface and Audio Front End Supports I2S interface High resolution D/A Converters for Stereo Audio playback Stereo analog input for stereo audio source Analog multiplexer for Stereo Audio FM Radio Recording Stereo to Mono Conversion maximum
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1.4
General Description
Figure 2 details the block diagram of MT6223. Based on a dual-processor architecture, MT6223 integrate both an ARM7EJ-S core and 2 digital signal processor cores. ARM7EJ-S is the main processor that is responsible for running 2G and 2.5G protocol software. Digital signal processors handle the MODEM algorithms as well as advanced audio functions. Except for some mixed-signal circuitries, the other building blocks in MT6223 are connected to either the microcontroller or one of the digital signal processor. Specifically, both MT6223 consist of the following subsystems: Microcontroller Unit (MCU) Subsystem - includes an ARM7EJ-S RISC processor and its accompanying memory management and interrupt handling logics. Digital Signal Processor (DSP) Subsystem - includes 2 DSP cores and their accompanying memory, memory controller, and interrupt controller. MCU/DSP Interface - where the MCU and the DSPs exchange hardware and software information. Microcontroller Peripherals - includes all user interface modules and RF control interface modules. Microcontroller Coprocessors - runs computing-intensive processes in place of Microcontroller. DSP Peripherals - hardware accelerators for GSM/GPRS/EGDE channel codec. Voice Front End - the data path for converting analog speech from and to digital speech. Audio Front End - the data path for converting stereo audio from stereo audio source Baseband Front End - the data path for converting digital signal from and to analog signal of RF modules. Timing Generator - generates the control signals related to the TDMA frame timing. Power, Reset and Clock subsystem - manages the power, reset, and clock distribution inside MT6223 LDOs, Power-on sequences, swicthes and SIM level shifters. Details of the individual subsystems and blocks are described in following Chapters.
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MT6223 : BB + PMIC SOC
MIC_0 MIC_1 VOICE_0 + VOICE_1 + Audio Path DAC Master DSP Coprocessors Coprocessors Coprocessors AUDIO_R STEREO_L STEREO_R TRX_I TRX_Q ADC ADC DAC DAC Bridge Aux ADC ADC Aux ADC Interrupt Controller PwrUp Seq JTAG Charger RGB DAC AFC TDMA Timer 32K OSC GPT SIM GPIO Alerter B2PSI BPI BSI WDT PWM Keypad Scanner Serial LCD UART Clock Generator System Clock 13/26MHz ARM7EJ-S MPU SECURITY ENGINE On-Chip SRAM LCD Controller LCD Camera BE (MT6223P Card I/F) Baseband Path Boot ROM MCU/DSP Interface DMA Controller External Memory Interface Flash SRAM Melody DAC Interrupt Controller Slave DSP Coprocessors Coprocessors Coprocessors Interrupt Controller ADC Patch Trap Unit Unit Memory Memory Patch Trap Unit Unit
DAC
Share RAM
AUDIO_L
6 LDOs Power Menagement Charger Switches AFC
BB LDOs BB LDOs BB LDOs RF LDO
APC
DAC
APC RTC
32KHz Crystal
Parallel RF Serial RF Reset Control Control
User Interface
Serial Port
Connectivity
Figure 2 MT6223 block diagram.
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2
2.1
Product Descriptions
Pin Outs
One type of package for this product, TFBGA 9mm * 9mm, 224-ball, 0.5mm pitch Package is offered. Pin-outs and the top view are illustrated in Figure 3 for this package. Outline and dimension of package is illustrated in Figure 4, while the definition of package is shown in Table 1.
C D E F G H J K L M N P R T U
VA RESET GATEDRV BATDET SIMRST URXD1 BAT_BACK AGND RSTCAP PWRKEY LED CHRIN SIMCLK UP UTXD2 VDDK UCTS1_B EINT3 EINT0 VDD33 EA19 EA18 EA17 EA16 URXD2 URTS1_B UTXD1 EINT2 KROW0 KROW3 EA22 EA21 EA20
C D E F G H J K L M N P R T U
AVDD_AFE
VCTXO
AU_FMINR
VMSEL AVDD_MB
EA15 VDD33_E MI VDD33_E VIBRATOR LED_G LED_B MI DGND VDDK
EA14
EA13
EA12
AU_MOUT AU_MOUT R L AU_FMINL
UFL
EA11
EA10
EA9
AU_OUT0 AU_OUT0 AU_MICBI AVSS_MBU _N _P AS_P FL DGND
EA8
EA7
EA6
AGND_AF AU_MICBI AU_VREF_ AU_VREF_ E AS_N NI AVSS_AFE PO AVDD_GS MRFRX VSS33 PGND LED_R DGND DGND TESTMOD E VSS33 EA2 EA1 EA0 EUB_B EA5 EA4 EA3
AU_VIN0_ AU_VIN0_ P N
AU_VIN1_ AU_VIN1_ AGND_RF AVDD_RF N BDLAQP AVSS_GSM RFRX APC AUXADIN0 AUXADIN1 AVDD_PLL P BDLAQN E BDLAIN E BDLAIP VSS33 VSS33
VSS33_EM VSS33_EM VSS33_EM I I I ELB_B ECS3_B ECS2_B ECS1_B
VSS33_LC VSS33_EM VSS33_EM D I I ECS0_B VDD33_E MI VDD33_E AUXADIN2 AUX_REF VDDK VDD33_L VDD33_E AVSS_RFE AFC_BYP BPI_BUS5 VDD33 VDD33 DAISYNC PWM JTDI VDDK LCD_D6 CD LCD_D2 MI LCD_WR_ AFC BPI_BUS0 BPI_BUS2 BPI_BUS6 BSI_DATA DAIRST ALERTER JTRST_B JTDO LCD_D7 B LCD_RST AVSS_PLL BPI_BUS1 BPI_BUS4 BPI_BUS7 BSI_CS0 DAICLK DAIPCMIN SYSRST_B DAIPCMO SYSCLK BPI_BUS3 BPI_BUS8 BPI_BUS9 BSI_CLK UT JRTCK JTCK LCD_D5 LCD_D4 LCD_D1 JTMS LCD_D8 LCD_D3 B LCD_D0 LCD_A0 EA25 ED3 LCD_CS0 _B WATCHDO G EWAIT ED0 ED2 ED4 ED5 ED8 ED7 ED6 MI ED11 ED10 ED9 ED14 ED13 ED12 EWR_B ERD_B ED15
LCD_RD_ LCD_CS1 B _B EADV_B ECLK ED1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Figure 3 Top View of MT6223 TFBGA 9mm*9mm 0.5mm pitch package
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Figure 4 Outlines and Dimension of TFBGA 9mm*9mm, 224-ball, 0. 5 mm pitch Package Body Size D 9.0 E 9.0 Ball Count N 224 Ball Pitch e 0.5 Ball Dia. b 0.275 Package Thk. A (Max.) 1.2 Stand Off A1 0.21 Substrate Thk. C 0.36
Table 1 Definition of TFBGA 9mm*9mm, 224-ball, 0.5 mm pitch Package (Unit: mm)
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2.2
Top Marking Definition
Security version (MT6223S)
S
Memory card MP3 version (MT6223P)
S
Security, Memory card MP3 version (MT6223SP)
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S
Non-security version (MT6223)
S
#
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DC Characteristics
2.2.1
Absolute Maximum Ratings
Prolonged exposure to absolute maximum ratings may reduce device reliability. Functional operation at these maximum ratings is not implied. Item IO power supply I/O input voltage Operating temperature Storage temperature Symbol VDD33 VDD33I Topr Tstg Min -0.3 -0.3 -20 -55 Max Unit VDD33+0.3 V VDD33+0.3 V 80 Celsius 125 Celsius
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2.3
BGA NAME
Pin Description
Dir PIN DESCRIPTION Analog Baseband Interface Aux Func.0 Aux Func.1 Aux Func.2 Aux Func.3 PU/PD Reset
Below pin description is identical for both MT6223.
F2 F1 E3 F3 G1 G2 G3 H2 H4 H3 J1 J2 K1 K2 L1 L2 L3 L4 N1 M2 M3 N2 N3 R1 P2
AU_MOUTL AU_MOUTR AU_FMINR AU_FMINL AU_OUT0_N AU_OUT0_P AU_MICBIAS_P AU_MICBIAS_N AU_VREF_PO AU_VREF_NI AU_VIN0_P AU_VIN0_N AU_VIN1_N AU_VIN1_P BDLAQP BDLAQN BDLAIN BDLAIP APC AUXADIN0 AUXADIN1 AUXADIN2 AUX_REF AFC AFC_BYP
Audio analog output left channel Audio analog output right channel FM radio analog input right channel FM radio analog input left channel Earphone 0 amplifier output (-) Earphone 0 amplifier output (+) Microphone bias supply (+) Microphone bias supply (-) Audio reference voltage (+) Audio reference voltage (-) Microphone 0 amplifier input (+) Microphone 0 amplifier input (-) Microphone 1 amplifier input (-) Microphone 1 amplifier input (+) Quadrature (Q+) baseband codec Quadrature (Q-) baseband codec Quadrature (I-) baseband codec Quadrature (I+) baseband codec Automatic power control DAC output Auxiliary ADC input 0 Auxiliary ADC input 1 Auxiliary ADC input 2 Reference voltage of Auxiliary ADC Automatic frequency control DAC output Automatic frequency control DAC bypass capacitance RF control circuitry
R2 T2 R3 U3 T3 P3 R4 T4 U4 U5 T5 R5 U6
BPI_BUS0 BPI_BUS1 BPI_BUS2 BPI_BUS3 BPI_BUS4 BPI_BUS5 BPI_BUS6 BPI_BUS7 BPI_BUS8 BPI_BUS9 BSI_CS0 BSI_DATA BSI_CLK
O O O O O O
RF hard-wire control bus bit 0 RF hard-wire control bus bit 1 RF hard-wire control bus bit 2 RF hard-wire control bus bit 3 RF hard-wire control bus bit 4 RF hard-wire control bus bit 5 BPI_BUS6 BPI_BUS7 BPI_BUS8 BPI_BUS9 GPIO20 GPIO21 GPIO22 GPIO23 XADMUX BSI_RFIN KCOL5 BSI_CS1 clk_out0 clk_out1 clk_out2 PD PD PU
IO RF hard-wire control bus bit 6 IO RF hard-wire control bus bit 7 IO RF hard-wire control bus bit 8 IO RF hard-wire control bus bit 9 O RF 3-wire control interface chip select 0
IO RF 3-wire control interface data output O RF 3-wire control interface clock output Digital Audio Interface (DAI)
T6 U7 T7
DAICLK DAIPCMOUT DAIPCMIN
IO DAI interface clock output IO DAI PCM data output IO DAI PCM data input
DAICLK DAIPCMOUT DAIPCMIN
GPIO15 GPIO16 GPIO17
EDICK EDIDAT
PU PD PU
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R6 P6
DAIRST DAISYNC
IO DAI reset signal input IO DAI frame synchronization input PWM Interface
DAIRST DAISYNC
GPIO18 GPIO19 EDIWS
PU PU
R7 P7
ALERTER PWM
IO Pulse-width modulated signal for buzzer IO Pulse-width modulated signal JTAG Interface
ALERTER PWM
GPIO24 GPIO25
PD PD
U8 R8 U9 P8 T9 R9
JRTCK JTRST_B JTCK JTDI JTMS JTDO
O I I I I O
JTAG test port returned clock output JTAG test port reset input JTAG test port clock input JTAG test port data input JTAG test port mode switch JTAG test port data output Parallel LCD Interface JTDI JTMS GPIO27 GPIO28 EINT5 EINT6 JTRST_B GPIO26 EINT4
PU PU PU PU PU
T10 R10 P10 U10 U11 T11 R11 U12 T12 R12 U13 T13 R13 R14 U14
LCD_D8 LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_RSTB LCD_WR_B LCD_RD_B LCD_D0 LCD_A0 LCD_CS0_B LCD_CS1_B
IO Parallel display interface Data 8 IO Parallel display interface Data 7 IO Parallel display interface Data 6 IO Parallel display interface Data 5 IO Parallel display interface Data 4 IO Parallel display interface Data 3 IO Parallel display interface Data 2 IO Parallel display interface Data 1 O O O Parallel display interface Reset Signal Parallel display interface Write Strobe Parallel display interface Read Strobe
LCD_D8 LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_RSTB LCD_WR_B LCD_RD_B LCD_D0 LCD_A0 LCD_CS0_B LCD_CS1_B
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 LCD_SCLK LCD_SDA LCD_SA0 LCD_SCE0_B LCD_SCE1_B EINT7
PD PD PD PD PD PD PD PD PD PU PU PD PU PU PU
IO Parallel display interface Data 0 O O O Parallel display interface address output Parallel display interface chip select 0 output Parallel display interface chip select 1 output External Memory Interface
U15 T15 U16 P13 T16 U17 T17 P14 R16 R17 P17 P16 P15 N17 N16 N15 M17 M16 M15
EADV_B EWAIT ECLK EA25 ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14
O O O
Flash, PSRAM and CellularRAM address valid, active low Flash, PSRAM and CellularRAM data ready Flash, PSRAM and CellularRAM clock
IO External memory CRE pin IO External memory data bus 0 IO External memory data bus 1 IO External memory data bus 2 IO External memory data bus 3 IO External memory data bus 4 IO External memory data bus 5 IO External memory data bus 6 IO External memory data bus 7 IO External memory data bus 8 IO External memory data bus 9 IO External memory data bus 10 IO External memory data bus 11 IO External memory data bus 12 IO External memory data bus 13 IO External memory data bus 14
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L17 L16 L15 L14 K17 K16 K15 K14 J17 J16 J15 J14 H17 H16 H15 G17 G16 G15 F17 F16 F15 E17 E16 E15 E14 D17 D16 D15 D14 C17 C16 C14 B17 B16
ED15 ERD_B EWR_B ECS0_B ECS1_B ECS2_B ECS3_B ELB_B EUB_B EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 EA17 EA18 EA19 EA20 EA21 EA22 EA23 EA24
IO External memory data bus 15 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O External memory read strobe, active low External memory write strobe, active low External memory chip select 0 External memory chip select 1 External memory chip select 2 External memory chip select 3 External memory lower byte strobe External memory upper byte strobe External memory address bus 0 External memory address bus 1 External memory address bus 2 External memory address bus 3 External memory address bus 4 External memory address bus 5 External memory address bus 6 External memory address bus 7 External memory address bus 8 External memory address bus 9 External memory address bus 10 External memory address bus 11 External memory address bus 12 External memory address bus 13 External memory address bus 14 External memory address bus 15 External memory address bus 16 External memory address bus 17 External memory address bus 18 External memory address bus 19 External memory address bus 20 External memory address bus 21 External memory address bus 22 External memory address bus 23 External memory address bus 24 System Miscellaneous EA0 GPIO30 EA25 PD GPIO52 MFIQ
J10 T8 T14 A17 A16
TESTMODE SYSRST_B WATCHDOG SRCLKENAI SRCLKENA
I I O I O
Factory test mode enable input System reset input active low Watchdog reset output, active low External VCTCXO enable input External VCTCXO enable output active high Keypad Interface WATCHDOG SRCLKENAI GPIO29 GPIO31
PD PU PD PD
A15 B15 A14 B14 A13 B13 C13
KCOL4 KCOL3 KCOL2 KCOL1 KCOL0 KROW4 KROW3
I I I I I O O
Keypad column 4 Keypad column 3 Keypad column 2 Keypad column 1 Keypad column 0 Keypad row 4 Keypad row 3
KCOL4 KCOL3 KCOL2 KCOL1 KCOL0 KROW4 KROW3
GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38
PU PU PU PU PU
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A12 B12 C12
KROW2 KROW1 KROW0
O O O
Keypad row 2 Keypad row 1 Keypad row 0 External Interrupt Inputs
KROW2 KROW1 KROW0
GPIO39 GPIO40 GPIO41
D12 B11 C11 D11
EINT0 EINT1 EINT2 EINT3
I I I I
External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 UART
EINT0 EINT1 EINT2 EINT3 GPIO42 GPIO43 MIRQ BT BE
PU PU PU PU
C10 D10 C9 A9 B9 C8 C7 D8
UTXD1 UCTS1_B URTS1_B UTXD3 URXD3 URXD2 URXD1 UTXD2
O I O
UART 1 transmit data UART 1 clear to send, active low UART 1 request to send, active low
UTXD1 UCTS1_B URTS1_B UTXD3 URXD3 URXD2 URXD1 UTXD2
GPIO44 GPIO45 GPIO46 GPIO47 GPIO48 GPIO49 GPIO50 GPIO51 UCTS2_B URTS2_B clk_out5 SCL SDA clk_out3 clk_out4
PU PU PU PU PU PU PU PU
IO UART 3 transmit data IO UART 3 receive data IO UART2 receive data I UART 1 receive data
IO UART2 transmit data Crystal and Clock Inputs
U1 A11 A10
SYSCLK XIN XOUT
13MHz or 26MHz system clock input 32.768 KHz crystal input 32.768 KHz crystal output SIM Card Interface
B5 C6 D6
SIMIO SIMRST SIMCLK
IO SIM Data Input / Outputs SIM card reset output SIM card clock output Charger and LED Driving Interface
D5 C4 G10 G9 H8 D4 G8
CHRIN GATEDRV LED_B LED_G LED_R LED VIBRATOR
Charger input
Vibrator driving output LDO Outputs
A5 A8 B8 A7 B7 B6 C1 E2
VSIM VRF VRF_SENSE VCORE VIO VM VA VCTXO
LDO output to SIM card RF LDO output RF LDO output sensing input Digital core voltage LDO output Digital I/O voltage LDO output External memory LDO output Analog LDO output Crystal or VCTCXO LDO output PMIC Miscellaneous
A3 B3 B2 A1 A2
VBAT_RF VBAT VBAT VBAT AVBAT
RF used battery voltage input Battery voltage input Battery voltage input Battery voltage input Battery voltage input
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D7 C5 A4 B4 C2 D2 B1 E4 D3
BAT_BACKUP BATDET BATSENSE ISENSE RESET RSTCAP VREF VMSEL PWRKEY Battery detection input Battery sense input Current sense input Powr on reset Reset capacitor connection point Reference voltage for PMIC Memory supply voltage level select input Power key press input Digital Power and Grounds
J8 H7 H11 H10 H9 K7 L8 K8 J11 J7 L9 K9 L10 K10 K11 N4 P9 D9 H14 D13 P4 P5 P11 P12 N14 M14 G14 F14
PGND DGND DGND DGND DGND VSS33 VSS33 VSS33 VSS33 VSS33 VSS33_EMI VSS33_EMI VSS33_EMI VSS33_EMI VSS33_EMI VDDK VDDK VDDK VDDK VDD33 VDD33 VDD33 VDD33_LCD VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI
PMIC ground PMIC ground PMIC ground PMIC ground PMIC ground Groud of chip digital part I/O circuitry Groud of chip digital part I/O circuitry Groud of chip digital part I/O circuitry Groud of chip digital part I/O circuitry Groud of chip digital part I/O circuitry Groud of external memory interface Groud of external memory interface Groud of external memory interface Groud of external memory interface Groud of external memory interface Supply voltage of digital core circuitry Supply voltage of digital core circuitry Supply voltage of digital core circuitry Supply voltage of digital core circuitry Supply voltage of digital part I/O circuitry Supply voltage of digital part I/O circuitry Supply voltage of digital part I/O circuitry Supply voltage of display interface I/O circuitry Supply voltage of external memory interface Supply voltage of external memory interface Supply voltage of external memory interface Supply voltage of external memory interface Supply voltage of external memory interface Analog Power and Grounds
K4 F4 J4 M4 E1 G4 T1 M1 P1
AVDD_RFE AVDD_MBUFL AVDD_GSMRFRX AVDD_PLL AVDD_AFE AVSS_MBUFL AVSS_PLL AVSS_GSMRFRX AVSS_RFE
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J3 D1 A6 H1 K3 B10
AVSS_AFE AGND AGND_RF AGND_AFE AGND_RFE AVDD_RTC Supply voltage of real time clock circuitry
Table 2 Pin Descriptions (Bolded types are functions at reset)
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Power Description
NAME IO Supply IO GND Core Supply Core GND Remark
AU_MOUTL AU_MOUTR AU_FMINR AU_FMINL AU_OUT0_N AU_OUT0_P AU_MICBIAS_P AU_MICBIAS_N AU_VREF_PO AU_VREF_NI AU_VIN0_P AU_VIN0_N AU_VIN1_N AU_VIN1_P BDLAQP BDLAQN BDLAIN BDLAIP APC AUXADIN0 AUXADIN1 AUXADIN2 AUX_REF AFC AFC_BYP
BPI_BUS0 BPI_BUS1 BPI_BUS2 BPI_BUS3 BPI_BUS4 BPI_BUS5 BPI_BUS6 BPI_BUS7 BPI_BUS8 BPI_BUS9 BSI_CS0 BSI_DATA BSI_CLK
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33
VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK
VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK
DAICLK DAIPCMOUT DAIPCMIN DAIRST DAISYNC
VDD33 VDD33 VDD33 VDD33 VDD33
VSS33 VSS33 VSS33 VSS33 VSS33
VDDK VDDK VDDK VDDK VDDK
VSSK VSSK VSSK VSSK VSSK
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ALERTER PWM
VDD33 VDD33
VSS33 VSS33
VDDK VDDK
VSSK VSSK
JRTCK JTRST_B JTCK JTDI JTMS JTDO
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
VSS33 VSS33 VSS33 VSS33 VSS33 VSS33
VDDK VDDK VDDK VDDK VDDK VDDK
VSSK VSSK VSSK VSSK VSSK VSSK
LCD_D8 LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_RSTB LCD_WR_B LCD_RD_B LCD_D0 LCD_A0 LCD_CS0_B LCD_CS1_B
VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD VDD33_LCD
VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33
VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK
VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK
EADV_B EWAIT ECLK EA25 ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 ERD_B
VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI
VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33
VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK
VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK
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EWR_B ECS0_B ECS1_B ECS2_B ECS3_B ELB_B EUB_B EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 EA17 EA18 EA19 EA20 EA21 EA22 EA23 EA24
VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI
VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33
VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK
VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK
TESTMODE SYSRST_B WATCHDOG SRCLKENAI SRCLKENA
VDD33 VDD33 VDD33_EMI VDD33 VDD33
VSS33 VSS33 VSS33 VSS33 VSS33
VDDK VDDK VDDK VDDK VDDK
VSSK VSSK VSSK VSSK VSSK
KCOL4 KCOL3 KCOL2 KCOL1 KCOL0 KROW4 KROW3 KROW2 KROW1
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33
VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK
VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK
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KROW0
VDD33
VSS33
VDDK
VSSK
EINT0 EINT1 EINT2 EINT3
VDD33 VDD33 VDD33 VDD33
VSS33 VSS33 VSS33 VSS33
VDDK VDDK VDDK VDDK
VSSK VSSK VSSK VSSK
UTXD1 UCTS1_B URTS1_B UTXD3 URXD3 URXD2 URXD1 UTXD2
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33 VSS33
VDDK VDDK VDDK VDDK VDDK VDDK VDDK VDDK
VSSK VSSK VSSK VSSK VSSK VSSK VSSK VSSK
SYSCLK XIN XOUT
AVDD_PLL AVDD_RTC AVDD_RTC
AVSS_PLL AVSS_RTC AVSS_RTC
AVDD_PLL AVDD_RTC AVDD_RTC
AVSS_PLL AVSS_RTC AVSS_RTC
SIMIO SIMRST SIMCLK
VSIM VSIM VSIM
CHRIN GATEDRV LED_B LED_G LED_R LED VIBRATOR
VSIM VRF VRF_SENSE VCORE VIO VM VA VCTXO
3.3/1.8V 2.8V
1.8/1.5V 2.8V 2.8/1.8V 2.8V 2.8V
VBAT_RF VBAT VBAT VBAT AVBAT BAT_BACKUP BATDET
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BATSENSE ISENSE RESET RSTCAP VREF VMSEL PWRKEY
PGND DGND DGND DGND DGND VSS33 VSS33 VSS33 VSS33 VSS33 VSS33_EMI VSS33_EMI VSS33_EMI VSS33_EMI VSS33_EMI VDDK VDDK VDDK VDDK VDD33 VDD33 VDD33 VDD33_LCD VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI VDD33_EMI TYP 1.8V TYP 1.8V TYP 1.8V TYP 1.8V TYP 2.8V TYP 2.8V TYP 2.8V 2.8V/1.8V 2.8V/1.8V 2.8V/1.8V 2.8V/1.8V 2.8V/1.8V 2.8V/1.8V
AVDD_RFE AVDD_MBUFL AVDD_GSMRFRX AVDD_PLL AVDD_AFE AVSS_MBUFL AVSS_PLL AVSS_GSMRFRX AVSS_RFE AVSS_AFE AGND
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AGND_RF AGND_AFE AGND_RFE AVDD_RTC
Table 3 Power Descriptions
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